View PE4302_236369.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Product Specification
PE4302
Product Description
The PE4302 is a high linearity, 6-bit RF Digital Step Attenuator "DSA" covering a 31.5 dB attenuation range in 0.5 dB steps. This 50-ohm RF DSA provides both parallel and serial CMOS control interface operates on a single 3-volt supply and maintains high attenuation accuracy over frequency and temperature. It also has a unique control interface that allows the user to select an initial attenuation state at power-up. The PE4302 exhibits very low insertion loss and low power consumption. This functionality is delivered in a 4x4mm QFN footprint. The PE4302 is manufactured in Peregrine's patented Ultra Thin Silicon (UTSi(R)) CMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. 50 RF Digital Attenuator 6-bit, 31.5 dB, DC - 4.0 GHz Features * Attenuation: 0.5 dB steps to 31.5 dB
* Flexible parallel and serial programming
interfaces
* Unique power-up state selection * Positive CMOS control logic * High attenuation accuracy and linearity
over temperature and frequency
* Very low power consumption * Single-supply operation * 50 impedance * Packaged in a 20 lead 4x4mm QFN
Figure 1. Functional Schematic Diagram
Switched Attenuator Array RF Input RF Output
Figure 2. Package Type
4x4mm -20 Lead QFN
Parallel Control Serial Control Power-Up Control
6
3
Control Logic Interface
2
Table 1. Electrical Specifications @ +25C, VDD = 3.0 V
Parameter
Operation Frequency Insertion Loss2 Attenuation Accuracy 1 dB Compression Input IP3
1,2 3
Test Conditions
Frequency
Minimum
DC
Typical
Maximum
4000
Units
MHz dB dB dB dBm dBm dB s
DC - 2.2 GHz Any Bit or Bit Combination DC 1.0 GHz 1.0 < 2.2 GHz 1 MHz - 2.2 GHz Two-tone inputs +18 dBm 50% control to 0.5 dB of final value 1 MHz - 2.2 GHz DC - 2.2 GHz
30 15 -
1.5 34 52 20 -
1.75 (0.10 + 3% of atten setting) (0.15 + 5% of atten setting) 1
Return Loss Switching Speed
Notes: 1. Device Linearity will begin to degrade below 1 Mhz 2. See Max input rating in Table 2 & Figures on Pages 2 to 4 for data across frequency. 3. Note Absolute Maximum in Table 3. Document No. 70/0056~02D www.psemi.com (c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 11
PE4302
Product Specification
Typical Performance Data (25C, VDD=3.0 V) Figure 3. Insertion Loss Figure 4. Attenuation at Major steps
0
35 31.5dB
-1
30 25
Insertion Loss (dB)
-40C 25C -3 85C
Normalized to Insertion Loss
Attenuation (dB)
-2
20 16dB 15 2dB 10 8dB 4dB 1dB 0.5dB
-4
-5
5 0 0 500 1000 1500 2000 2500 3000 3500 4000 0
-6
500
1000
1500
2000
2500
3000
3500
4000
RF Frequency (MHz)
RF Frequency (MHz)
Figure 5. Input Return Loss at Major Attenuation Steps
0
Figure 6. Output Return Loss at Major Attenuation Steps
0
-10
-10
-20 S11 (dB) S22 (dB)
-20
-30
16dB
-30
31.5dB
-40
31.5dB
-40
-50 0 500 1000 1500 2000 2500 3000 3500 4000
-50 0 500 1000 1500 2000 2500 3000 3500 4000
RF Frequency (MHz)
RF Frequency (MHz)
(c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 11
Document No. 70/0056~02D UltraCMOSTM RFIC Solutions
PE4302
Product Specification
Typical Performance Data (25C, VDD=3.0 V) Figure 7. Attenuation Error Vs. Frequency Figure 8. Attenuation Error Vs. Attenuation Setting
0.5
2
0 31.5 (dB) 0 Attenuation Error (dB) 10Mhz 500Mhz 1000Mhz -0.5 1500Mhz 2000Mhz -1 -8 2200Mhz
Attenuation Error (dB)
-2
-4
-6
-10 0 500 1000 1500 2000 2500 3000 3500 4000
-1.5 0 5 10 15 20 25 30 35 40
RF Frequency (MHz)
Attenuation Setting (dB)
Figure 9. Attenuation Error Vs. Attenuation Setting
0.6
Figure 10. Attenuation Error Vs. Attenuation Setting
0.4
0.4
0.2 0 1000Mhz, -40C -0.2 1000Mhz, 25C 1500Mhz, -40C -0.6 10Mhz, 85C 1000Mhz, 85C 1490Mhz, 25C 1490Mhz, 85C
Attenuation Error (dB)
0.2
500Mhz, -40C 0 10Mhz, 25C -0.2 500Mhz, 25C
Attenuation Error (dB)
10Mhz, -40C
-0.4
-0.4
500Mhz, 85C
-0.8 -1
-0.6 0 5 10 15 20 25 30 35 40
0
5
10
15
20
25
30
35
40
Attenuation Setting (dB)
Attenuation Setting (dB)
Document No. 70/0056~02D www.psemi.com
(c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 11
PE4302
Product Specification
Typical Performance Data (25C, VDD=3.0 V) Figure 11. Attenuation Error Vs. Frequency Figure 12. Input IP3 Vs. Frequency
0.5 2200Mhz, -40C
60 55 50 2000Mhz, -40C Input IP3 (dBm) 45 40 35 30 2000Mhz, 85C 25 .5dB 2dB 8dB 31.5dB 0dB 1dB 4dB 16dB
0 Attenuation Error (dB)
-0.5
2200Mhz, 25C 2000Mhz, 25C 2200Mhz, 85C
-1
-1.5 0 5 10 15 20 25 30 35 40
20 0 500 1000 1500 2000 2500 3000
Attenuation Setting (dB)
RF Frequency (MHz)
Figure 13. Input 1 dB Compression
40
35 1dB Compression (dBm)
30
25
20 0dB 15 0.5dB 10 0 500 1000 1500 2000 2500 3000 2dB 8dB 31.5dB 1dB 4dB 16dB
RF Frequency (MHz)
(c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 11
Document No. 70/0056~02D UltraCMOSTM RFIC Solutions
PE4302
Product Specification
Figure 14. Pin Configuration (Top View)
GND C0.5 C1 C2 C4
Table 3. Absolute Maximum Ratings
Symbol
VDD VI
Parameter/Conditions
Power supply voltage Voltage on any input Storage temperature range Operating temperature range Input power (50) ESD voltage (Human Body Model)
Min
-0.3 -0.3 -65 -40
Max
4.0 VDD+ 0.3 150 85 24 500
Units
V V C C dBm V
20
19
18
17
16
C16 RF1 Data Clock LE
1 2 3 4 5 10
15
C8 RF2 P/S Vss/GND GND
TST TOP PIN VESD
20-lead QFN 4x4mm
Exposed Solder Pad
14 13 12 11
6
7
8
9
Table 4. DC Electrical Specifications
Parameter
VDD Power Supply Voltage IDD Power Supply Current
PUP1
PUP2
VDD
VDD
GND
Min
2.7
Typ
3.0
Max
3.3 100
Units
V A V
Table 2. Pin Descriptions
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Paddle
Pin Name
C16 RF1 Data Clock LE VDD PUP1 PUP2 VDD GND GND Vss/GND P/S RF2 C8 C4 C2 GND C1 C0.5 GND
Description
Attenuation control bit, 16dB (Note 4). RF port (Note 1). Serial interface data input (Note 4). Serial interface clock input. Latch Enable input (Note 2). Power supply pin. Power-up selection bit, MSB. Power-up selection bit, LSB. Power supply pin. Ground connection. Ground connection. Negative supply voltage or GND connection(Note 3) Parallel/Serial mode select. RF port (Note 1). Attenuation control bit, 8 dB. Attenuation control bit, 4 dB. Attenuation control bit, 2 dB. Ground connection. Attenuation control bit, 1 dB. Attenuation control bit, 0.5 dB. Ground for proper operation
Digital Input High Digital Input Low Digital Input Leakage
0.7xVDD 0.3xVDD 1
V A
Exposed Solder Pad Connection The exposed solder pad on the bottom of the package must be grounded for proper device operation. Electrostatic Discharge (ESD) Precautions When handling this UltraCMOSTM device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rate specified in Table 3. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOSTM devices are immune to latch-up. Switching Frequency The PE4302 has a maximum 25kHz switching rate. Resistor on Pin 1 & 3 A 10 k resistor on the inputs to Pin 1 & 3 (see Figure 16) will eliminate package resonance between the RF input pin and the two digital inputs. Specified attenuation error versus frequency performance is dependent upon this condition.
(c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 11
Note 1: Both RF ports must be held at 0 VDC or DC blocked with an external series capacitor. 2: Latch Enable (LE) has an internal 100 k resistor to VDD. 3: Connect pin 12 to GND to enable internal negative voltage generator. Connect pin 12 to VSS (-VDD) to bypass and disable internal negative voltage generator. 4. Place a 10 k resistor in series, as close to pin as possible to avoid frequency resonance. Document No. 70/0056~02D www.psemi.com
PE4302
Product Specification
Programming Options
Parallel/Serial Selection Either a parallel or serial interface can be used to control the PE4302. The P/S bit provides this selection, with P/S=LOW selecting the parallel interface and P/S=HIGH selecting the serial interface. Parallel Mode Interface The parallel interface consists of five CMOScompatible control lines that select the desired attenuation state, as shown in Table 5. The parallel interface timing requirements are defined by Figure 18 (Parallel Interface Timing Diagram), Table 9 (Parallel Interface AC Characteristics), and switching speed (Table 1). For latched parallel programming the Latch Enable (LE) should be held LOW while changing attenuation state control values, then pulse LE HIGH to LOW (per Figure 18) to latch new attenuation state into device. For direct parallel programming, the Latch Enable (LE) line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct Mode is ideal for manual control of the device (using hardwire, switches, or jumpers).
Clock, and Latch Enable (LE). The Data and Clock inputs allow data to be serially entered into the shift register, a process that is independent of the state of the LE input. The LE input controls the latch. When LE is HIGH, the latch is transparent and the contents of the serial shift register control the attenuator. When LE is brought LOW, data in the shift register is latched. The shift register should be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data. The timing for this operation is defined by Figure 17 (Serial Interface Timing Diagram) and Table 8 (Serial Interface AC Characteristics). Power-up Control Settings The PE4302 always assumes a specifiable attenuation setting on power-up. This feature exists for both the Serial and Parallel modes of operation, and allows a known attenuation state to be established before an initial serial or parallel control word is provided. When the attenuator powers up in Serial mode (P/ S=1), the six control bits are set to whatever data is present on the six parallel data inputs (C0.5 to C16). This allows any one of the 64 attenuation settings to be specified as the power-up state. When the attenuator powers up in Parallel mode (P/ S=0) with LE=0, the control bits are automatically set to one of four possible values. These four values are selected by the two power-up control bits, PUP1 and PUP2, as shown in Table 6 (Power-Up Truth Table, Parallel Mode).
Table 5. Truth Table
P/S
0 0 0 0 0 0 0 0
C16
0 0 0 0 0 0 1 1
C8
0 0 0 0 0 1 0 1
C4
0 0 0 0 1 0 0 1
C2
0 0 0 1 0 0 0 1
C1
0 0 1 0 0 0 0 1
Attenuation C0.5 State
0 1 0 0 0 0 0 1 Reference Loss 0.5 dB 1 dB 2 dB 4 dB 8 dB 16 dB 31.5 dB
Table 6. Parallel PUP Truth Table
P/S
0 0 0 0
LE
0 0 0 0 1
PUP2
0 1 0 1 X
PUP1
0 0 1 1 X
Attenuation State
Reference Loss 8 dB 16 dB 31 dB Defined by C0.5-C16
Note: Not all 64 possible combinations of C0.5-C16 are shown in table
Serial Interface The serial interface is a 6-bit serial-in, parallel-out shift register buffered by a transparent latch. It is controlled by three CMOS-compatible signals: Data,
0
Note: Power up with LE=1 provides normal parallel operation with C0.5-C16, and PUP1 and PUP2 are not active.
(c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 11
Document No. 70/0056~02D UltraCMOSTM RFIC Solutions
PE4302
Product Specification
Evaluation Kit
The Digital Attenuator Evaluation Kit board was designed to ease customer evaluation of the PE4302 Digital Step Attenuator. J9 is used in conjunction with the supplied DC cable to supply VDD, GND, and -VDD. If use of the internal negative voltage generator is desired, then connect -VDD (Black banana plug) to ground. If an external -VDD is desired, then apply -3V. J1 should be connected to the parallel port of a PC with the supplied ribbon cable. The evaluation software is written to operate the DSA in serial mode, so Switch 7 (P/S) on the DIP switch SW1 should be ON with all other switches off. Using the software, enable or disable each attenuation setting to the desired combined attenuation. The software automatically programs the DSA each time an attenuation state is enabled or disabled. To evaluate the Power Up options, first disconnect the parallel ribbon cable from the evaluation board. The parallel cable must be removed to prevent the PC parallel port from biasing the control pins. During power up with P/S=1 high and LE=0 or P/ S=0 low and LE=1, the default power-up signal attenuation is set to the value present on the six control bits on the six parallel data inputs (C0.5 to C16). This allows any one of the 64 attenuation settings to be specified as the power-up state. During power up with P/S=0 high and LE=0, the control bits are automatically set to one of four possible values presented through the PUP interface. These four values are selected by the two power-up control bits, PUP1 and PUP2, as shown in the Table 6. Resistor on Pin 1 & 3 A 10 k resistor on the inputs to Pin 1 & 3 (Figure 16) will eliminate package resonance between the RF input pin and the two digital inputs. Specified attenuation error versus frequency performance is dependent upon this condition.
Document No. 70/0056~02D www.psemi.com
Figure 15. Evaluation Board Layout
Figure 16. Evaluation Board Schematic
C0.5 C1 20 19 18
C2 C4 17 C2 16 C4
C5
C1
J4
C16 1 Z=50 Ohm DATA 10k CLK LE
1 2 3 4 5
GND
10k
C16
C8
15 14 13 12 11
C8 Z=50 Ohm PS 1
J5
RFin DATA
MLPQ4X4 U1 PUP1 PUP2
RFout PS
SMA
SMA
VDD_D
CLK VDD LE
Vss/GND GND GND
VDD
PUP1 PUP2
100 pF
Note: Resistors on pins 1 and 3 are required to avoid package resonance and meet error specifications over frequency.
(c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 11
10
6
7
8
9
PE4302
Product Specification
Figure 17. Serial Interface Timing Diagram
LE
Table 7. 6-Bit Attenuator Serial Programming Register Map
Clock
B5 C16
Data MSB LSB
B4 C8
B3 C4
B2 C2
B1 C1
B0 C0.5
MSB (first in)
tLESUP tLEPW
LSB (last in)
tSDSUP
tSDHLD
Figure 18. Parallel Interface Timing Diagram
LE
Parallel Data C16:C0.5
tPDSUP
tLEPW
tPDHLD
Table 8. Serial Interface AC Characteristics
VDD = 3.0 V, -40 C < TA < 85 C, unless otherwise specified Symbol
fClk tClkH tClkL tLESUP tLEPW
Table 9. Parallel Interface AC Characteristics
VDD = 3.0 V, -40 C < TA < 85 C, unless otherwise specified Symbol
tLEPW tPDSUP tPDHLD
Parameter
Serial data clock frequency (Note 1) Serial clock HIGH time Serial clock LOW time LE set-up time after last clock falling edge LE minimum pulse width
Min
Max
10
Unit
MHz ns ns ns ns
Parameter
LE minimum pulse width Data set-up time before rising edge of LE Data hold time after falling edge of LE
Min
10 10 10
Max
Unit
ns ns ns
30 30 10 30
Serial data set-up time 10 ns tSDSUP before clock rising edge Serial data hold time 10 ns tSDHLD after clock falling edge Note: fClk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk specification.
(c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 11
Document No. 70/0056~02D UltraCMOSTM RFIC Solutions
PE4302
Product Specification
Figure 19. Package Drawing
4.00 INDEX AREA 2.00 X 2.00 -B2.00
2.00 0.25 C -A0.10 C 0.08 C 0.020 0.20 REF EXPOSED PAD & TERMINAL PADS SEATING PLANE 0.80 4.00 -C2.00 TYP 0.50 TYP 0.55 2.00 1.00
5 11
0.435 0.18 1.00 EXPOSED PAD 0.23 1 0.10 CAB 2.00
1 15 20 16 6 10
0.435
0.18
4.00
DETAIL A
DETAIL A
2
1. Dimension applies to metallized terminal and is measured between 0.25 and 0.30 from terminal tip. 2. Coplanarity applies to the exposed heat sink slug as well as the terminals. 3. Dimensions are in millimeters.
Document No. 70/0056~02D www.psemi.com
(c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 11
PE4302
Product Specification
Figure 20. Marking Specifications
4302 YYWW ZZZZZ
YYWW = Date Code ZZZZZ = Last five digits of PSC Lot Number
Figure 21. Tape and Reel Drawing
Table 10. Ordering Information
Order Code 4302-01 4302-02 4302-00 4302-51 4302-52 Part Marking 4302 4302 PE4302-EK 4302 4302 Description PE4302-20MLP 4x4mm-75A PE4302-20MLP 4x4mm-3000C PE4302-20MLP 4x4mm-EK PE4302G-20MLP 4x4mm-75A PE4302G-20MLP 4x4mm-3000C Package 20-lead 4x4mm QFN 20-lead 4x4mm QFN Evaluation Kit Green 20-lead 4x4mm QFN Green 20-lead 4x4mm QFN Shipping Method 75 units / Tube 3000 units / T&R 1 / Box 75 units / Tube 3000 units / T&R
(c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 10 of 11
Document No. 70/0056~02D UltraCMOSTM RFIC Solutions
PE4302
Product Specification
Sales Offices
United States Peregrine Semiconductor Corp.
9450 Carroll Park Drive San Diego, CA 92121 Tel 1-858-731-9400 Fax 1-858-731-9499
Japan Peregrine Semiconductor K.K.
5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: 011-81-3-3502-5211 Fax: 011-81-3-3502-5213
Europe Peregrine Semiconductor Europe
Batiment Maine 13-15 rue des Quatre Vents F- 92380 Garches, France Tel: 011- 33-1-47-41-91-73 Fax : 011-33-1-47-41-91-73
China Peregrine Semiconductor
28G, Times Square, No. 500 Zhangyang Road, Shanghai, 200122, P.R. China Tel: 011-86-21-5836-8276 Fax: 011-86-21-5836-7652
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS is a trademark of Peregrine Semiconductor Corp.
Preliminary Specification
The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice).
Document No. 70/0056~02D www.psemi.com
(c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 11 of 11

▲Up To Search▲

Price & Availability of PE4302

	To Download PE4302 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .